HP Implementing HP BladeSystem Solutions - HP0-S35 FREE EXAM DUMPS QUESTIONS & ANSWERS

You are troubleshooting a specific problem on a Windows Server 2008 R2 need to quickly verify which Microsoft KB patches have been installed. How can you do this?
Correct Answer: C Vote an answer
What is a possible reason for the Unknown port status in Fabric-A in the screenshot shown?
Correct Answer: D Vote an answer
You are experiencing packet loss with low latency networks. Which value(s) should you customize so that the various HP SIM polling tasks complete in the shortest amount of time?
Correct Answer: D Vote an answer
You are configuring HP Integrity Virtual Machines on an HP Inegrity BL8x0c i2 blade server system based on the Intel Itanium processor 9300 series. You plan to use the default 10 Gb Ethernet adapters with jumbo frame support. Which memory sizing rule must be used for the HPUX guest OS?
Correct Answer: D Vote an answer
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What is the maximum number of hard drives that can be installed in a D2200sb Storage Blade?
Correct Answer: D Vote an answer
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An HP Blc 4x QDR InfiniBand switch is intalled in Bays 3 and 4 in a c7000 enclosure. What is the maximum number of downlink ports that it provides for connections to blade server?
Correct Answer: D Vote an answer
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Which statements are correct about HP SmartDrive carrier authentication? (Select two)
Correct Answer: B,C Vote an answer
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An engineer installs four HP Virtual Connect Flex-10 10 Gb Ethernet modules into a c7000 enclosure. What is required to enable all Ethernet NICs on all servers to have access to any Virtual Connect Ethernet module uplink port?
Correct Answer: D Vote an answer
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Which KVM is assigned Master Status in a cascaded configuration?
Correct Answer: A Vote an answer
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What is required to configure an HP ProLiant BL460c Gen8 memory in lock-step mode?
Correct Answer: B Vote an answer
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When installing a Modular Cooling System (MCS) G2, which safely considerations must be
implemented? (Select two)
Correct Answer: A,C Vote an answer
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An HP BladeSystem c7000 Insight Display backlight is flashing. What can cause this?
Correct Answer: B Vote an answer
What should you before replacing a drive in a HP P4000 hot-swap storage system?
Correct Answer: A Vote an answer
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HOTSPOT
Match each technology to its description.

Correct Answer:

Explanation:

http://h71000.www7.hp.com/doc/83final/b9073_90111/apas13.html The LPMC monitor, within the Support Tools Manager (STM) diagnostics, generates Information events for all cache errors that are detected. After three errors (Threshold) have been detected on a processor in 1440 minutes, or a 24-hour period of time (Period), the monitor deactivates that particular processor, marks it for deconfiguration on the next system reboot, and generates a SERIOUS event. After the failed processor is deactivated, the LPMC monitor attempts to activate one of the inactive Instant Capacity processors, if any are available. This method ensures the processing power of the system is unchanged.
A default value of "three" is assigned to Threshold, except for the PCX-W+ family of processors, which has a value of "five" assigned. The default value assigned to a Period is 1440 minutes, or 24 hours, in all possible processor configurations.
An inactive processor under warranty or support automatically replaces a failed processor. HP also services and replaces any failed processor.
http://www.techrepublic.com/whitepapers/mca-error-recovery-hp-ux-feature-for-recovering-frommachinecheck-aborts/354967
HP Integrity servers provide superior reliability and availability. Nevertheless, even the best of computers can occasionally experience hardware problems that lead to unplanned downtime. Some of these problems are caused by transient events such as an alpha particle strike on memory, cache, or a processor data structure.
Intel Itanium-based servers support an advanced architecture that allows the system to contain, correct, and signal machine check errors. Many of these errors are corrected by the platform without operating system intervention. When the platform cannot correct an error, it will be handed off to the operating system. To further enhance the superior reliability of HP Integrity servers, the HP-UX MCA Error Recovery feature adds the ability to recover from some of these Machine Check Aborts (MCAs).
http://dl.acm.org/citation.cfm?id=1057740 Soft errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits. Both combinational and sequential logic circuits are expected to be affected. Many different latch designs to prevent soft errors due to particle strikes on the latch nodes have been proposed. We review these designs and compare them based on their robustness and their power and performance overheads. We also propose new latch designs, the best of which is vulnerable only to a single-event, multiple-upset without any delay overhead and consumes only 40% power of a standard latch. We expect this work will help designers to select latches for applications where soft error is an important design metric.
http://en.wikipedia.org/wiki/Montecito_(processor)
Advanced compensation for errors in cache, for reliable operation under mission-critical workloads. This was code-named Pellston technology during development, and has recently been renamed Intel Cache Safe Technology
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